The present invention generally relates to an image display apparatus of an active-matrix type and particularly to an image display apparatus designed for holding a signal voltage written or inputted during a given selected period over a time span extending beyond that selected period for the purpose of controlling the electro-optical characteristics of the display elements by the above-mentioned signal voltage. In more particular, the present invention is concerned with an image display apparatus which is capable of displaying images with a multiplicity of gradation levels (gray scale levels) by controlling the period for which the above-mentioned signal voltage represented by a binary-level voltage signal is to be held in accordance with the level of a picture signal to be displayed.
In recent years, with the advent of the highly sophisticated information society, there exists an increasing demand for personal computers, portable information terminals, information communication equipment and/or combined apparatuses or systems thereof. In these apparatuses or systems, a display device implemented in a thin and light-weight structure and capable of responding at a high speed is advantageously suited. To this end, the display device implemented by employing organic LED (light emitting diode) elements (also called OLED in abbreviation) of spontaneous light emission type or the like has been developed and used for practical applications. For better understanding of the present invention, brief description will first be made of a conventional display device known heretofore. FIG. 1A of the accompanying drawings shows a circuit structure of a pixel (picture element) in an organic LED display apparatus. Referring to the figure, a first thin-film transistor (TFT) Tsw 23 (hereinafter also referred to simply as the first TFT 23) is provided at an intersection between a gate line (or gate wire) 22 and a data bus line 21. Connected to the first TFT Tsw 23 are a capacitor Cs 25 for storing a data current and a second thin-film transistor (TFT) Tdr 24 (hereinafter also referred to simply as the second TFT 24) for controlling the current allowed to flow to an organic LED (OLED) 26. FIG. 1B is a waveform diagram illustrating waveforms of voltages for driving the pixel components mentioned above. Referring to FIG. 1B, a voltage conforming to a data signal Vsig is applied to a gate electrode of the second TFT 24 via the first TFT 23 which is turned on in response to a gate voltage Vgh 28. Conductivity of the second TFT 24 is determined in dependence on the signal voltage applied to the gate thereof. A voltage Vdd applied to a current supply line 27 is divided between the TFT and the organic LED element 26 constituting a load element, as a result of which the current flowing to the organic LED element 26 is determined. In this conjunction, it is noted that with the arrangement in which the data signal Vsig can assume a multiplicity of values in terms of analog signal, it is required that the characteristics of the second TFTs be homogeneous over the display area of the display apparatus. However, in practice, difficulty is encountered in satisfying the above requirement because of non-homogeneousness of the electric characteristics of the TFTs having the respective active layers formed of poly crystal silicon (i.e., not single crystal silicon).
With a view to solving the problem mentioned above, such a digital drive scheme has been proposed according to which the second TFT is employed as a switch so that the current which flows to the organic LED element can assume binary values or levels, i.e., on- and off-levels, respectively. Display with the gradation can be realized by controlling the time during which the current is allowed to flow. This sort of arrangement is described, for example, in Japanese Patent Application Laid-Open Publication No. 214060/1998 (JP-A-10-214060). FIG. 2 of the accompanying drawings is a view for illustrating a drive scheme disclosed in the above publication. In the figure, positions of vertical scanning lines are taken along the ordinate with the time taken along the abscissa for a single frame. According to the driving principle taught in the above publication, the single frame period is divided into four subframes, wherein each of the subframes includes a vertical scanning period having a common duration throughout the subframes and a light emission period whose duration differs from one to another subframe, being weighted 1, 2, . . . , 24=64.
With the drive scheme in which the vertical scanning period and the light emission period are separated from each other as described above, the proportion of the time for light emission within one frame is shortened because the vertical scanning period can not naturally be utilized for the light emission. Accordingly, the vertical scanning period has to be shortened in order to ensure the light emission period. However, since the first thin-film transistor (TFT) Tsw is turned on during a time approximately corresponding to a quotient of division of the vertical scanning period by the number (m) of the vertical scanning lines (i.e., vertical scanning period/vertical scanning line number (m)), the vertical scanning period of a sufficient duration is necessarily required in order to ensure the above-mentioned on-time of the first TFT Tsw when taking into consideration the wiring capacitance, resistance and the like factors inherent to the active matrix. By way of example, in the case of the display with eight subframes, it is expected that the vertical scanning period on the order of about 1 ms is required for each subframe. In that case, the time available for the light emission is about 8 ms which corresponds to a half of the frame. Additionally, it is required that the single vertical scanning has to be carried out at a rate about sixteen times as high the ordinary scanning, giving rise to problems.
The problems mentioned above can be solved by multiplexing the vertical scanning so that the vertical scanning and the light emission can proceed simultaneously. In that case, the drive scheme will be such as illustrated in FIG. 3. More specifically, shown in FIG. 3 is an example of three-bit drive, wherein situation in which three vertical scannings and display are in progress is illustrated. The basic concept underlying this drive scheme has first been disclosed in Image System Study Data 11-4, xe2x80x9cGENERATION OF HALF-TONE ANIMATION BY AC-TYPE PLASMA DISPLAYxe2x80x9d published by the Institute of Television Engineers of Japan (Mar. 12, 1973), and an example of application of this concept to an active-matrix liquid crystal is suggested in Patent Publication No. 2954329 as well. However, in the case of the liquid crystal device proposed in the above-mentioned patent publication, high response performance is necessarily required in practice. Such being the circumstances and as a result of development of the technique concerning the analog display with the response rate slower than the frame period, the structure for actually implementing the above-mentioned drive scheme has not seen the light yet.
On the other hand, in the present state of the art, the organic LED display based on the active-matrix scheme which is advantageously suited for the digital drive with high response rate is now available, as described hereinbefore, as a result of which there has arisen a demand for a structure or arrangement capable of driving the organic LED display for practical applications.
In the light of the state of the art described above, it is contemplated with present invention to realize a structure of the image display apparatus of an active-matrix type which can generate displays through digital drive by multiplexing the vertical scanning for allowing the display period and the vertical scanning period to proceed simultaneously.
Thus, it is an object of the present invention to provide an image display apparatus which can generate or display bright and high-quality images for practical application.
Another object of the present invention is to provide an image display apparatus which can be implemented at low cost while mitigating a load imposed on a vertical drive circuit.
In view of the above and other objects which will become apparent as the description proceeds, there is provided according to an embodiment of the present invention an image display apparatus of an active-matrix type arranged such that digital data including a number of bits is applied to a number of sequential circuits which is at least equal to the number of bits, to thereby determine voltage state for a single vertical scanning line on the basis of result of logical operation performed on the outputs of the sequential circuits. Further, the arrangement mentioned above is multiplexed such that the digital data are applied in parallel to line latches provided in a number at least equal to the number of bits to be outputted in synchronism with multiplexed vertical scannings.
Furthermore, according to another embodiment of the present invention, an image display apparatus includes a display unit and a drive circuit unit formed on a substrate. The image display apparatus is designed to display an image signal of digital data having a number n of bits with a number of gradation levels determined by the bit number n, wherein the drive circuit unit comprises a number of sequential circuits which is not smaller than the bit number n at the least and logic circuits connected to output sides of the sequential circuits, respectively.
Furthermore, the drive circuit unit includes a vertical drive circuit, wherein the vertical drive circuit comprises a number of sequential circuits which is not smaller than the bit number n at the least and logic circuits connected to output sides of the sequential circuits, respectively.
According to yet another embodiment of the present invention, an image display apparatus includes a display unit and a drive circuit unit formed on a substrate. The image display apparatus is designed to display an image signal of digital data having a number n of bits with a number of gradation levels determined by the bit number n, wherein the drive circuit unit is comprised of line data latch circuits in a number not smaller than the bit number n at the least and so arranged as to control the drive circuit unit in dependence on results of sequential additions of logical signals representing products of bit-based outputs of the line data latch circuits and a control signal for dividing the horizontal scanning period.
Additionally, the drive circuit unit includes a horizontal drive circuit, wherein the horizontal drive circuit is comprised of line data latch circuits in a number not smaller than the bit number n at the least and so arranged as to control the drive circuit unit in dependence on results of sequential additions of logical signals representing products of bit-based outputs of the line data latch circuits and a control signal for dividing horizontal scanning period.
The above and other objects, features and attendant advantages of the present invention will more easily be understood by reading the following description of the preferred embodiments thereof taken, only by way of example, in conjunction with the accompanying drawings.